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| S71NS-J Stacked Multi-Chip Product (MCP) 110 nm CMOS 1.8 Volt-only Simultaneous Read/Write, Burst Mode Multiplexed Flash Memory with pSRAM S71NS-J Cover Sheet Data Sheet (Advance Information) Notice to Readers: This document states the current technical specifications regarding the Spansion product(s) described herein. Each product described herein may be designated as Advance Information, Preliminary, or Full Production. See Notice On Data Sheet Designations for definitions. Publication Number S71NS-J_00 Revision 03 Issue Date October 10, 2006 Data Sheet (Advance Information) Notice On Data Sheet Designations Spansion Inc. issues data sheets with Advance Information or Preliminary designations to advise readers of product information or intended specifications throughout the product life cycle, including development, qualification, initial production, and full production. In all cases, however, readers are encouraged to verify that they have the latest information before finalizing their design. The following descriptions of Spansion data sheet designations are presented here to highlight their presence and definitions. Advance Information The Advance Information designation indicates that Spansion Inc. is developing one or more specific products, but has not committed any design to production. Information presented in a document with this designation is likely to change, and in some cases, development on the product may discontinue. Spansion Inc. therefore places the following conditions upon Advance Information content: "This document contains information on one or more products under development at Spansion Inc. The information is intended to help you evaluate this product. Do not design in this product without contacting the factory. Spansion Inc. reserves the right to change or discontinue work on this proposed product without notice." Preliminary The Preliminary designation indicates that the product development has progressed such that a commitment to production has taken place. This designation covers several aspects of the product life cycle, including product qualification, initial production, and the subsequent phases in the manufacturing process that occur before full production is achieved. Changes to the technical specifications presented in a Preliminary document should be expected while keeping these aspects of production under consideration. Spansion places the following conditions upon Preliminary content: "This document states the current technical specifications regarding the Spansion product(s) described herein. The Preliminary status of this document indicates that product qualification has been completed, and that initial production has begun. Due to the phases of the manufacturing process that require maintaining efficiency and quality, this document may be revised by subsequent versions or modifications due to changes in technical specifications." Combination Some data sheets contain a combination of products with different designations (Advance Information, Preliminary, or Full Production). This type of document distinguishes these products and their designations wherever necessary, typically on the first page, the ordering information page, and pages with the DC Characteristics table and the AC Erase and Program table (in the table notes). The disclaimer on the first page refers the reader to the notice on this page. Full Production (No Designation on Document) When a product has been in production for a period of time such that no changes or only nominal changes are expected, the Preliminary designation is removed from the data sheet. Nominal changes may include those affecting the number of ordering part numbers available, such as the addition or deletion of a speed option, temperature range, package type, or VIO range. Changes may also include those needed to clarify a description or to correct a typographical error or incorrect specification. Spansion Inc. applies the following conditions to documents in this category: "This document states the current technical specifications regarding the Spansion product(s) described herein. Spansion Inc. deems the products to have been in sufficient production volume such that subsequent versions of this document are not expected to change. However, typographical or specification corrections, or modifications to the valid combinations offered may occur." Questions regarding these document designations may be directed to your local Spansion sales office. ii S71NS-J October 10, 2006 S71NS-J_00_03 S71NS-J Stacked Multi-Chip Product (MCP) 110 nm CMOS 1.8 Volt-only Simultaneous Read/Write, Burst Mode Multiplexed Flash Memory with pSRAM Data Sheet (Advance Information) Features Single 1.8 volt read, program and erase (1.7 to 1.95 V) Multiplexed Data and Address for reduced I/O count - A15-A0 multiplexed as DQ15-DQ0 - Addresses are latched by AVD# control input when CE# low Simultaneous Read/Write operation - Data can be continuously read from one bank while executing erase/program functions in other bank - Zero latency between read and write operations Package - 56-ball Very Thin FBGA Product Selector Guide MCP S71NS032JA0 S71NS032J80 Flash S29NS032J S29NS032J pSRAM 16 Mb 8 Mb pSRAM Type Mux pSRAM 2 Mux pSRAM 1 pSRAM Read Asynchronous only Asynchronous only OPN S71NS032JA0BJWRT S71NS032J80BJWRA General Description The products covered by this document are listed in the table below Document S29NS-J 8 Mb Multiplexed pSRAM Type 1 16Mb Multiplexed pSRAM Type 2 (Asynchronous only) Publication Identification Number S29NS-J_00 muxpsram_06 muxpsram_05 Publication Number S71NS-J_00 Revision 03 Issue Date October 10, 2006 This document contains information on one or more products under development at Spansion LLC. The information is intended to help you evaluate this product. Do not design in this product without contacting the factory. Spansion LLC reserves the right to change or discontinue work on this proposed product without notice. Data Sheet (Advance Information) 1. MCP Block Diagram VCC VCCQ RESET# ACC CE# OE# WE# CLK A19-A16 A20 VSS VCC VSSQ VCCQ F-RDY/R-WAIT A/DQ15 - A/DQ0 RDY Flash Memory AVD# WAIT LB# pSRAM UB# CRE CS# VSS Note: A19 is shared for S71NS032JA0, but flash only for S71NS032J80. VSSQ 2 S71NS-J S71NS-J_00_03 October 10, 2006 Data Sheet (Advance Information) 2. Connection Diagram 1 A NC B Flash, pSRAM Shared C NC D F-RDY/ R-WAIT E VCCQ F VSS G A/DQ15 A/DQ14 VSSQ H NC J RFU R-CE# R-CRE RFU NC A/DQ5 A/DQ4 A/DQ11 A/DQ10 VCCQ A/DQ1 A/DQ0 A/DQ7 A/DQ6 A/DQ13 A/DQ12 A/DQ3 A/DQ2 A/DQ9 A/DQ8 OE# A16 A20 AVD# RFU F-RST# F-WP# A-18 F-CE# VSSQ pSRAM Only A21 VSS CLK VCC WE# F-ACC A19 A17 RFU Flash Only RFU R-LB# R-UB# RFU NC Reserved for Future Use NC No Connect 2 3 4 5 6 7 8 9 10 11 12 13 14 Legend K NC NC MCP S71NS032JA0 S71NS032J80 Flash-only Address A20 A20-A19 Shared Address A19:A16 ADQ15:ADQ0 A18:A16 ADQ15:ADQ0 S71NS-J_00_03 October 10, 2006 S71NS-J 3 Data Sheet (Advance Information) 3. Input/Output Descriptions Signal R-UB# R-LB# A21-A16 ADQ15-ADQ0 R-CE# F-CE# OE# WE# VCC VSS NC RDY pSRAM Upper Byte Control pSRAM Lower Byte Control Address Inputs Multiplexed Address/Data input/output pSRAM Chip Select Input Flash Chip Enable Input. Asynchronous relative to CLK for the Burst mode. Output Enable Input. Asynchronous relative to CLK for the Burst mode. Write Enable Input. Device Power Supply (1.7 V-1.95 V). Ground No Connect; not connected internally Ready output; indicates the status of the Burst read. VOL= data invalid. WAIT# pin of pSRAM is shared with Flash RDY pin for synchronous pSRAM. Clock input. The first rising edge of CLK in conjunction with AVD# low latches address input and activates burst mode operation. After the initial word is output, subsequent rising edges of CLK increment the internal address counter. CLK should remain low during asynchronous access. CLK is present on MuxpSRAM Type 3, but not on MuxpSRAM Type 2. As a result, it is a shared signal on S71NS064JA0, but a flash-only signal on S71NS032J. Address Valid input. Indicates to device that the valid address is present on the address inputs (address bits A15-A0 are multiplexed, address bits A22-A16 are address only). VIL = for asynchronous mode, indicates valid address; for burst mode, causes starting address to be latched on rising edge of CLK. VIH= device ignores address inputs Hardware reset input. VIL= device resets and returns to reading array data At 12 V, accelerates programming; automatically places device in unlock bypass mode. At VIL, disables program and erase functions. Should be at VIH for all other conditions. Command Register Enable of pSRAM I/O Power Supply (1.7 V to 1.95 V) I/O Ground X X X X X X X X X X X X X X X X X Description Flash RAM X X X X X CLK X X AVD# X X F-RST# F-ACC R-CRE VCCQ VSSQ X X X X X 4 S71NS-J S71NS-J_00_03 October 10, 2006 Data Sheet (Advance Information) 4. Ordering Information The order number (Valid Combination) is formed by the following: S71NS 032 J A0 BJ W RT 0 PACKING TYPE 0 = Tray 2 = 7-inch Tape and Reel 3 = 13-inch Tape and Reel ADDITIONAL ORDERING OPTIONS See Valid Combinations Table TEMPERATURE RANGE W = Wireless (-25C to +85C) For Industrial (-40C to +85C), contact local sales office PACKAGE TYPE BJ = Very Thin Fine-Pitch BGA Lead (Pb)-Free LF35 Package pSRAM DENSITY A0 = 16 Megabit (1M x 16-Bit) FLASH PROCESS TECHNOLOGY J = 110 nm Floating Gate Technology FLASH DENSITY 064 = 64 Megabit (4 M x 16-Bit) 032 = 32 Megabit (2M x 16-Bit) DEVICE FAMILY S71NS = Stacked Multi-Chip Product, Simultaneous Read/Write, Burst Mode Flash Memory with Multiplexed I/O 1.8-Volt Operation, Top Boot Sectors, and pSRAM Table 4.1 Valid Combinations Base OPN S71NS Density 032 Process Technology J A0 pSRAM Density 80 BJ W RT Package Type Temperature Options RA 0, 2, 3 Packing Type S71NS-J_00_03 October 10, 2006 S71NS-J 5 Data Sheet (Advance Information) 5. 5.1 Physical Dimensions NLB056--56-Ball Very Thin Fine Pitch Ball Grid Array (FBGA) 9.2 x 8.0 mm Package D 0.10 C (2X) 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A D1 eD SE 7 E1 E eE INDEX MARK PIN A1 CORNER 9 K J HGFEDCBA B 7 TOP VIEW 0.10 C (2X) SD PIN A1 CORNER BOTTOM VIEW 0.20 C A A2 A1 6 C 0.08 C SIDE VIEW b 56X 0.15 M C A B 0.08 M C NOTES: PACKAGE JEDEC DxE SYMBOL A A1 A2 D E D1 E1 MD ME n Ob eE eD SD / SE 0.25 NLB 056 N/A 9.20 mm x 8.00 mm PACKAGE MIN --0.20 0.85 NOM ------9.20 BSC. 8.00 BSC. 4.50 BSC. 6.50 BSC. 10 14 56 0.30 0.50 BSC. 0.50 BSC 0.25 BSC. A2 ~ A13,B1 ~ B14 C1,C2,C5,C6,C9,C10,C13,C14 D1,D2,D13,D14,E1,E2,E13,E14,F1,F2,F13,F14 G1,G2,G13,G14,H1,H2,H5,H6,H9,H10,H13,H14 J1 ~ J14, K2 ~ K13 1. 2. 3. NOTE PROFILE BALL HEIGHT BODY THICKNESS BODY SIZE BODY SIZE MATRIX FOOTPRINT MATRIX FOOTPRINT MATRIX SIZE D DIRECTION MATRIX SIZE E DIRECTION BALL COUNT 0.35 BALL DIAMETER BALL PITCH BALL PITCH SOLDER BALL PLACEMENT DEPOPULATED SOLDER BALLS 9 8. 7 6 4. 5. DIMENSIONING AND TOLERANCING METHODS PER ASME Y14.5M-1994. ALL DIMENSIONS ARE IN MILLIMETERS. BALL POSITION DESIGNATION PER JEP95, SECTION 4.3, SPP-010. e REPRESENTS THE SOLDER BALL GRID PITCH. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D" DIRECTION. SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE "E" DIRECTION. n IS THE NUMBER OF POPULTED SOLDER BALL POSITIONS FOR MATRIX SIZE MD X ME. DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL DIAMETER IN A PLANE PARALLEL TO DATUM C. SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A AND B AND DEFINE THE POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW. WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE OUTER ROW SD OR SE = 0.000. WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE OUTER ROW, SD OR SE = e/2 "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED BALLS. A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK MARK, METALLIZED MARK INDENTATION OR OTHER MEANS. MAX 1.20 --0.97 10. OUTLINE AND DIMENSIONS PER CUSTOMER REQUIREMENT. 3507\ 16-038.22 \ 7.14.5 6 S71NS-J S71NS-J_00_03 October 10, 2006 Data Sheet (Advance Information) 6. 6.1 Revision History Revision 01 (March 2, 2006) Initial release. 6.2 Revision 02 (April 21, 2006) Added the S71NS032JA0 Updated the MCP Block Diagram Updated the Connection Diagram notes Updated the Input/Output Descriptions 6.3 Revision 03 (October 10, 2006) Added the S71NS032J80 Removed the S71NS064JA0 Colophon The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for any use that includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for any use where chance of failure is intolerable (i.e., submersible repeater and artificial satellite). Please note that Spansion will not be liable to you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country, the prior authorization by the respective government entity will be required for export of those products. Trademarks and Notice The contents of this document are subject to change without notice. This document may contain information on a Spansion product under development by Spansion. Spansion reserves the right to change or discontinue work on any product without notice. The information in this document is provided as is without warranty or guarantee of any kind as to its accuracy, completeness, operability, fitness for particular purpose, merchantability, non-infringement of third-party rights, or any other warranty, express, implied, or statutory. Spansion assumes no liability for any damages of any kind arising out of the use of the information in this document. Copyright (c) 2006 Spansion Inc. All Rights Reserved. Spansion, the Spansion logo, MirrorBit, ORNAND, and combinations thereof are trademarks of Spansion Inc. Other names are for informational purposes only and may be trademarks of their respective owners. S71NS-J_00_03 October 10, 2006 S71NS-J 7 |
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